1. Field of the Invention
The present invention relates to a power-down circuit useful in, for example, a liquid crystal display (LCD) to prevent an abnormal image from appearing when the power supply of the display is shut off.
2. Description of the Related Art
Recent LCDs generally have built-in power supply circuits that use charge pumps, for example, to generate a comparatively high voltage such as twelve volts (12 V) from a comparatively low logic power supply voltage such as 3 V. The high voltage is divided to obtain the voltages that are applied to individual picture elements in the liquid crystal panel to express gradations of lightness and darkness specified by image data. When the power of the LCD is switched on or off, the image data become erratic, so a preprogrammed sequence of operations is carried out in the built-in power supply circuit to assure that unintended high voltages are not applied to the liquid crystal panel.
The preprogrammed power-on or power-off sequence may fail to be executed properly if power is lost unexpectedly because of, say, an electrical outage, actuation of a circuit breaker, or a drop in battery voltage. In these cases, the capacitors used in the charge pump circuit may retain high voltages that continue to be applied to the display panel, causing an abnormal image to appear, until the charge is dissipated by natural discharge. Continued application of high voltages after loss of power may also degrade the liquid crystal.
The built-in power supply therefore includes circuitry for discharging the charge pump when the main power supply is shut off. FIG. 1 shows a typical example of such circuitry, disclosed in Japanese Patent Application Publication No. 2003-295841. This circuit discharges a pair of capacitors 531, 535 that hold LCD driving voltages V1 and V5, which are output from a segment driver 512-1 and a common driver 512-2, respectively. The discharging circuit comprises a charge shunting section 560, a voltage detecting section 570, and a voltage shunting section 580.
The voltage detecting section 570 has a capacitor 574 connected between ground (GND) and a node N1 that receives the main power supply voltage VCC through a resistor 571. The function of the capacitor 574 is to keep node N1 near the VCC level for a while after the power supply is shut off. The voltage detecting section 570 also has an inverter 600 connected between ground and node N1, the inverter 600 comprising a p-channel metal-oxide-semiconductor (PMOS) transistor 572 and an n-channel metal-oxide-semiconductor (NMOS) transistor 573 that receive the power supply voltage VCC as their gate inputs.
The voltage shunting section 580 comprises a resistor 581 and an NMOS transistor 582 connected in series between the power supply VCC and ground. The charge shunting section 560 comprises NMOS transistors 561 and 565 with sources connected to ground and drains connected to capacitors 531 and 535. The gates of NMOS transistors 582, 561, and 565 receive the output of the inverter 600.
In this circuit, when the main power supply is on and VCC is above the threshold voltage of NMOS transistor 573, the output of the inverter 600 is at the low (ground) level, so NMOS transistors 561 and 565 are turned off.
When the main power supply is shut off, VCC falls toward ground, but node N1 lingers near the normal VCC level (e.g., 3 V) because of the charge stored in capacitor 574, so PMOS transistor 572 turns on and the output of the inverter 600 goes high. NMOS transistors 561 and 565 now turn on and start discharging capacitors 531 and 535. Since NMOS transistor 582 is also turned on, the main power supply is discharged and VCC falls rapidly to the ground level. The higher voltages V1 and V5 fall rapidly enough to prevent an obviously abnormal display from appearing on the LCD panel and prevent degradation of the liquid crystal.
A problem with the conventional circuit shown in FIG. 1 is that while capacitors 531 and 535 are being discharged, the gate potential of the discharging transistors 561, 565 is also being drawn down toward the rapidly-falling VCC level. The discharging transistors may therefore turn off before the driving voltages V1 and V5 reach the ground level. The final levels of the driving voltages depend on the parameters of the resistors, capacitors, and transistors in FIG. 1, but if the discharging transistors have a high threshold voltage, which is desirable for preventing sub-threshold leakage, the driving voltages may be left at about the one-volt level when the discharging transistors turn off, causing unwanted dim artifacts to persist on the display.